Yield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford
by Moore
1988304 pages
Taylor & Francis·1 editions
Loading Description
Tags
NewBookshelves
0 readersNo users with this book on their shelves. Maybe you could be the first.
Threads
0 discussionsQuotes
0 quotesReviews
0 reviewsNo reviews yet. Add your review.
Lists
0 listsNo lists containing this book.
Purchasable Editions
1 editionsThe Amazon links are affiliate links
Yield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford (1988)
Yield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford (1988)
Taylor & Francis, Adam Hilger
Taylor & Francis, Adam Hilger
Hardcover
ISBN 10: 085274398X
ISBN 13: 9780852743980